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74F323 Octal Universal Shift/Storage Register
April 1988 Revised August 1999
74F323 Octal Universal Shift/Storage Register with Synchronous Reset and Common I/O Pins
General Description
The 74F323 is an 8-bit universal shift/storage register with 3-STATE outputs. Its function is similar to the 74F299 with the exception of Synchronous Reset. Parallel load inputs and flip-flop outputs are multiplexed to minimize pin count. Separate serial inputs and outputs are provided for Q0 and Q7 to allow easy cascading. Four operation modes are possible: hold (store), shift left, shift right and parallel load.
Features
s Common parallel I/O for reduced pin count s Additional serial inputs and outputs for expansion s Four operating modes: shift left, shift right, load and store s 3-STATE outputs for bus-oriented applications
Ordering Code:
Order Number 74F323SC 74F323PC Package Number M20B N20A Package Description 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter "X" to the ordering code.
Logic Symbols
Connection Diagram
IEEE/IEC
(c) 1999 Fairchild Semiconductor Corporation
DS009517
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74F323
Unit Loading/Fan Out
Pin Names CP DS0 DS7 S0, S1 SR OE1, OE2 I/O0-I/O7 Q0, Q7 Description Clock Pulse Input (Active Rising Edge) Serial Data Input for Right Shift Serial Data Input for Left Shift Mode Select Inputs Synchronous Reset Input (Active LOW) 3-STATE Output Enable Inputs (Active LOW) Multiplexed Parallel Data Inputs 3-STATE Parallel Data Outputs Serial Outputs U.L. HIGH/LOW 1.0/1.0 1.0/1.0 1.0/1.0 1.0/2.0 1.0/1.0 1.0/1.0 3.5/1.083 150/40 (33.3) 50/33.3 Input IIH/IIL Output IOH/IOL 20 A/-0.6 mA 20 A/-0.6 mA 20 A/-0.6 mA 20 A/-1.2 mA 20 A/-0.6 mA 20 A/-0.6 mA 70 A/-0.65 mA -3 mA/24 mA (20 mA) -1 mA/20 mA
Functional Description
The 74F323 contains eight edge-triggered D-type flip-flops and the interstage logic necessary to perform synchronous reset, shift left, shift right, parallel load and hold operations. The type of operation is determined by S0 and S1 as shown in the Mode Select Table. All flip-flop outputs are brought out through 3-STATE buffers to separate I/O pins that also serve as data inputs in the parallel load mode. Q0 and Q7 are also brought out on other pins for expansion in serial shifting of longer words. A LOW signal on SR overrides the Select inputs and allows the flip-flops to be reset by the next rising edge of CP. All other state changes are also initiated by the LOW-to-HIGH CP transition. Inputs can change when the clock is in either state provided only that the recommended setup and hold times, relative to the rising edge of CP, are observed. A HIGH signal on either OE 1 or OE2 disables the 3-STATE buffers and puts the I/O pins in the high impedance state. In this condition the shift, load, hold and reset operations can still occur. The 3-STATE buffers are also disabled by HIGH signals on both S0 and S1 in preparation for a parallel load operation.
Logic Diagram
Mode Select Table
Inputs SR S1 L H H H H X H L H L S0 CP X H H L L Response

X
Synchronous Reset; Q0-Q7 = LOW Parallel Load; I/On Qn Shift Right; DS0 Q0, Q0 Q1, etc. Shift Left; DS7 Q7, Q7 Q6, etc. Hold
H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial = LOW-to-HIGH transition
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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74F323
Absolute Maximum Ratings(Note 1)
Storage Temperature Ambient Temperature under Bias Junction Temperature under Bias VCC Pin Potential to Ground Pin Input Voltage (Note 2) Input Current (Note 2) Voltage Applied to Output in HIGH State (with VCC = 0V) Standard Output 3-STATE Output Current Applied to Output in LOW State (Max) ESD Last Passing Voltage (Min) twice the rated IOL (mA) 4000V -0.5V to VCC -0.5V to +5.5V -65C to +150C -55C to +125C -55C to +150C -0.5V to +7.0V -0.5V to +7.0V -30 mA to +5.0 mA
Recommended Operating Conditions
Free Air Ambient Temperature Supply Voltage 0C to +70C +4.5V to +5.5V
Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. Note 2: Either voltage limit or current limit is sufficient to protect inputs.
DC Electrical Characteristics
Symbol VIH VIL VCD VOH Parameter Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage Output HIGH Voltage 10% VCC 10% VCC 5% VCC 5% VCC VOL IIH IBVI IBVIT ICEX VID IOD IIL IOS IZZ ICCH ICCL ICCZ Output LOW Voltage Input HIGH Current Input HIGH Current Breakdown Test Input HIGH Current Breakdown (I/O) Output HIGH Leakage Current Input Leakage Test Output Leakage Circuit Current Input LOW Current Output Short-Circuit Current Bus Drainage Test Power Supply Current Power Supply Current Power Supply Current 68 68 68 -60 4.75 3.75 -0.6 -1.2 -150 500 95 95 95 10% VCC 10% VCC 2.5 2.4 2.7 2.7 0.5 0.5 5.0 7.0 0.5 50 V A A mA A V A mA mA mA A mA mA mA Min Max Max Max Max 0.0 0.0 Max Max Max 0.0V Max Max Max V Min Min 2.0 0.8 -1.2 Typ Max Units V V V Min VCC Conditions Recognized as a HIGH Signal Recognized as a LOW Signal IIN = -18 mA IOH = -1 mA (Q0, Q7) IOH = -3 mA (I/On) IOH = -1 mA (Q0, Q7) IOH = -3 mA (I/On) IOL = 20 mA (Q0, Q7) IOL = 24 mA (I/On) VIN = 2.7V VIN = 7.0V (Non I/O Inputs) VIN = 5.5V (I/O Inputs) VOUT = VCC IID = 1.9 A All Other Pins Grounded VIOD = 150 mV All Other Pins Grounded VIN = 0.5V VIN = 0.5V VOUT = 0V VOUT = 5.25V VO = HIGH VO = LOW VO = HIGH Z (CP, DS0, DS7, SR, OE1, OE2) (S0, S1)
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74F323
AC Electrical Characteristics
TA = +25C Symbol Parameter Min fMAX tPLH tPHL tPLH tPHL tPZH tPZL tPHZ tPLZ tPZH tPZL tPHZ tPLZ Output Enable Time Sn to I/On Output Disable Time Sn to I/On Output Disable Time Maximum Input Frequency Propagation Delay CP to Q0 or Q7 Propagation Delay CP to I/On Output Enable Time 70 4.0 4.5 3.5 4.0 3.5 4.0 2.0 1.0 3.5 4.0 2.5 1.0 VCC = +5.0V CL = 50 pF Typ 100 7.0 6.5 7.0 8.5 6.0 7.0 4.5 4.0 8.0 8.0 9.0 9.0 8.0 10.0 6.0 5.5 9.0 10.0 6.0 5.5 Max TA = 0C to +70C VCC = +5.0V CL = 50 pF Min 70 4.0 4.5 3.5 4.0 3.5 4.0 2.0 1.0 3.5 4.0 2.5 1.5 8.5 8.5 10.0 10.0 9.0 11.0 7.0 6.5 10.0 11.0 7.0 6.5 ns ns ns ns Max MHz Units
AC Operating Requirements
TA = +25C Symbol Parameter VCC = +5.0V Min tS(H) tS(L) tH(H) tH(L) tS(H) tS(L) tH(H) tH(L) tS(H) tS(L) tH(H) tH(L) tW(H) tW(L) Setup Time, HIGH or LOW S0 or S1 to CP Hold Time, HIGH or LOW S0 or S1 to CP Setup Time, HIGH or LOW I/On, DS0, DS 7 to CP Hold Time, HIGH or LOW I/On, DS0, DS 7 to CP Setup Time, HIGH or LOW SR to CP Hold Time, HIGH or LOW SR to CP CP Pulse Width HIGH or LOW 8.5 8.5 0 0 5.0 5.0 2.0 2.0 10.0 10.0 0 0 5.0 5.0 Max TA = 0C to +70C VCC = +5.0V Min 8.5 8.5 0 0 5.0 5.0 2.0 2.0 10.0 10.0 0 0 5.0 5.0 ns ns ns ns Max Units
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74F323
Physical Dimensions inches (millimeters) unless otherwise noted
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide Package Number M20B
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74F323 Octal Universal Shift/Storage Register
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Package Number N20A
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com 6 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com

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